The present invention relates to a method for fabricating a semiconductor device with an MOS structure.
In recent years, as the number of semiconductor devices integrated on a single chip has been tremendously increased, respective components of each semiconductor device have been drastically downsized. On the other hand, semiconductor devices are increasingly required to operate at an even higher speed and to demonstrate further improved reliability.
A semiconductor device with an MOS structure has heretofore been used for various type of electronic units and is also expected to find broader and broader applications from now on.
Hereinafter, a conventional method for fabricating a semiconductor device, more particularly a method for forming a gate electrode for an MOS transistor, will be described with reference to FIGS. 23(a) and 23(b).
First, as shown in FIG. 23(a), a field oxide film 12 is formed by a LOCOS technique so as to surround a transistor-forming region 11 on a silicon substrate 10. Thereafter, the surface of the silicon substrate 10 is thermally oxidized, thereby forming a silicon dioxide film 13 on the surface of the silicon substrate 10. Next, a doped polysilicon film (not shown) is deposited by a CVD process over the entire surface of the silicon substrate 10, and then a resist pattern (not shown, either) is defined on the polysilicon film. Subsequently, using the resist pattern as a mask, the polysilicon film is etched to form a gate electrode 14. And source/drain regions 15, 16 are formed.
Then, as shown in FIG. 23(b), exposed portions of the silicon dioxide film 13, which are located on right- and left-hand sides of the gate electrode 14, are removed, thereby forming a gate insulating film 17. Thereafter, an insulating film 18 is deposited over the entire surface of the silicon substrate 10 and planarized. Next, contact holes 19, 20 and 21 are formed in the insulating film 18 to reach the gate electrode 14, source region 15 and drain region 16, respectively. Then, a conductive material is deposited to fill in these contact holes 19, 20 and 21 and to slightly protrude upward therefrom. In this manner, electrode layers 22, 23 and 24 are formed so as to be interconnected to the gate electrode 14, source region 15 and drain region 16, respectively.
As can be seen, according to the conventional method for fabricating a semiconductor device, when the gate electrode 14 is formed by etching a conductive film (i.e., the polysilicon film), the silicon dioxide film 13 is used as an etch stopper.
However, the larger the number of semiconductor devices integrated is, the thinner the gate insulating film of an MOS transistor tends to be. Thus, according to the conventional method, i.e., if a gate electrode is formed by patterning a conductive film using an insulating film to be a gate insulating film as an etch stopper, not only the conductive film to be etched away, but also the gate insulating film are removed unintentionally. As a result, the reliability of the gate insulating film deteriorates.
To make a semiconductor device with an MOS structure operate at a higher speed, the thickness of a gate electrode should be increased such that the gate electrode has its resistance reduced. However, if the thickness of the gate electrode is increased, i.e., if the aspect ratio of the gate electrode (which is a ratio of the thickness of the gate electrode to the width thereof) is increased, then the conductive film should be etched to a greater depth. Accordingly, it is more difficult to end the etching process exactly at the upper surface of the insulating film to be the gate insulating film. Stated otherwise, if the gate insulating film should be thin, then the aspect ratio of the gate electrode cannot be large and the resistance of the gate electrode cannot be sufficiently reduced. Nevertheless, when the aspect ratio of the gate electrode is set high, the aspect ratio of a contact hole, which is used to interconnect a doped layer formed within a semiconductor substrate, i.e., source/drain region, to an interconnection layer, should also be high. In such a situation, the process steps of forming the contact hole and filling in the contact hole with a conductive material cannot be performed just as originally designed, thus decreasing the reliability of the semiconductor device.